The present invention relates to a high definition television (HDTV) having a picture-in-picture (PIP) function, and more particularly, to a HDTV system having a PIP function for implementing a PIP image by reconstructing an intraframe image with low resolution.
A general HDTV system will now be described with reference to accompanying drawings.
FIG. 1 is an overall block diagram of a general HDTV system. As shown, the HDTV system includes a tuner & channel decoder 1 for receiving an RF signal transmitted from a broadcasting station and decoding the same in the unit of packets, a depacketizer 2 for receiving and separating a signal generated from tuner & channel decoder 1 into a video bit stream and an audio bit stream to then be output, a video decoder 3 for decoding the video bit stream of the signals generated from depacketizer 2, and a display 4 for outputting the image reconstructed by being decoded in video decoder 3.
The operation of the HDTV system having the aforementioned configuration will now be described.
Tuner & channel decoder 1 having received the RF signal via an antenna decodes the received signal into data of the packet unit to then be output. Depacketizer 2 having received the decoded signal from tuner & channel decoder 1 separates the signal into a video hit stream and an audio bit stream then be output. Video decoder 3 having received the video bit stream generated in depacketizer 2 decodes the video bit stream and reconstruct a video to then be output to display 4.
Here, video decoder 3 of FIG. 1 will be described in more detail with reference to FIG. 2.
FIG. 2 is a detailed block diagram of video decoder 3 in a general HDTV system. As shown, video decoder 3 includes a video buffer 5 for temporarily storing the video bit stream generated in depacketizer 2 shown in FIG. 1, a variable length decoder (VLD) 6 for reading the bit stream stored in video buffer 5 and decoding the signal, an inverse quantizer (Q.sup.-) 7 for inversely quantizing the decoded data output from VLD 6, an inverse discrete cosine transform unit (IDCT) 8 for releasing the DCT-compressed signal generated in inverse quantizer 7 and output the difference value from the immediately previous picture in the unit of pixels, an adder 9 for adding the pixel data generated in IDCT 8 with the previous frame data motion-compensated by a motion compensator to be described later, a motion compensator 10 for receiving I and P signals among the outputs of adder 9 and compensating the motion thereof, and a video display processor (VDP) 13 for converting a signal generated in adder 9, i.e., a perfect picture data composed of a luminance signal and a chrominance signal, into R, G and B signals to then be displayed.
Here, motion compensator 10 is composed of a frame memory A (FMA) and a frame memory B (FMB) each for storing a sheet of a perfect picture data immediately prior to compensation.
Referring to FIG. 2, first, input video bit stream is temporarily stored in image buffer 5 and the bit stream is read and decoded in VLD 6, thereby outputting coefficient and motion vector data, respectively.
The output coefficient data becomes pixel data via inverse quantizer 7 and IDCT 8.
Here, the pixel data output from IDCT 8 is the difference value data from the previous picture not from the perfect picture data.
The data is added with the data of the previous frame motion-compensated by motion compensator 10, in adder 9, thereby completing a final perfect picturen data.
The perfect picture is stored in FMA 11 and FMB 12 by each portion of one frame.
Also, the signal of the perfect picture is converted into R, G and B signals which can be displayed on VDP 13 to then be output thereto.
However, in the general HDTV system shown in FIGS. 1 and 2, since two HDTV decoders are required for implementing a PIP image, the circuit becomes complex and the cost is increased accordingly.